1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device and a non-volatile semiconductor storage system, and particularly, to a non-volatile semiconductor storage device and a system with a refresh function of memory cells to improve reliability of data.
2. Description of the Related Art
One of the well-known non-volatile semiconductor storage devices is a NAND cell type flash memory. The NAND cell type flash memory includes a memory cell array including a plurality of NAND cell units. Each NAND cell unit includes a plurality of memory cells connected in series and two selection transistors connected to both ends thereof. The memory cell holds, in an erase state, data “1” having a negative threshold voltage. In a data write operation, a floating gate is injected with electrons to rewrite data “0” having a positive threshold voltage. The NAND cell type flash memory may change the threshold voltage only from a lower value to a higher value in a data write operation, and may change the threshold voltage in the reverse direction (from a higher value to a lower value) only by an erase operation per a block.
However, a probability of fail bit occurrence in a memory cell array is increasing greatly, as the memory cell is miniaturized, thus lowering the yield of non-volatile memory chips. In considering this situation, a memory with an error correction circuit using an error correction code (ECC) in order to guarantee data reliability of a memory cell has been proposed (for example, see Patent Document 1: JP 2002-251884 (Paragraph 0026-0030 etc.))
Moreover, a technology for performing a refresh operation is also known (for example, see Patent Documents 2: JP 3176019 B1). The refresh operation to stored data is accomplished by performing periodical data rewrite, performing data rewrite to other areas, an additional write-verify operation or the like, in order to lowering a fail-bit occurrence rate.
Performing a refresh operation in all memory areas results in a long time for finishing a refresh operation. In addition, it might give an unnecessary stress to areas with a small amount of fail bits. Accordingly, in the technology disclosed in the Patent Document 2, a number (a number of times) of error corrections conducted is fed back from an error-correction circuit, and a refresh operation is carried out only in areas where a number of error corrections conducted is close to a limit correctable by an error correction code.
An error-correction circuit using iterative decoding method with soft-decision information as an input (a decoder circuit with an LDPC code or the like) has a splendid error correction ability. However, it does not count the number of errors corrected. Moreover, in an error-correction process using iterative decoding method based on soft-decision information, it is difficult to judge whether the number of error corrections conducted is close to a limit correctable by an error correction code.